The present invention relates generally to semiconductor manufacturing processes and, more particularly, to a method for forming suspended transmission line structures in back end of line (BEOL) processing of semiconductor devices.
Semiconductor integrated circuits typically are formed by MOS (metal oxide semiconductor) or by bipolar transistors that are integrated at a top planar major surface of a silicon chip. Electrical interconnections between various transistors, as well as between certain transistors and access pins located along the periphery of the chip, have typically taken the form of two (or more) “levels” of interconnections, i.e., electrically conducting lines in the form of metallization stripes running along two (or more) essentially planar surfaces that are oriented mutually parallel to, and are insulated from, both each other and the top planar surface of the chip by suitable insulating layers. Interconnection vias (windows) in the insulating layers are provided wherever needed in accordance with the desired circuit interconnections.
In particular, microstrip structures are used primarily in radio frequency (RF) CMOS/SiGe chips, where wiring is not dense. Generally, microstrip structures provide fairly good isolation of the signal from lossy substrate material underneath. As illustrated in FIG. 1(a), a typical microstrip transmission line structure 10 includes a signal transmission line 12, an underlying ground plane 14 for shielding, and an interlayer dielectric material (ILD) 16 therebetween. Since the shielding 14 and signal transmission line 12 are fabricated as standard interconnect components, they are encapsulated by the dielectric material 16. Examples of such dielectric material include, for example, silicon dioxide (SiO2), SiCOH, SiLK, FSG, USG, among others. The dielectric constant of such materials generally ranges from about 2.5 to about 4.1.
On the other hand, coplanar waveguides are commonly used where wiring density is relatively high, such as in CMOS chips, for example, where it is difficult to create an explicit return path below the signal line. The only way to reliably return the signal is to also use the same routing metal level as the one used for the signal wire. Thus, as shown in FIG. 1(b), a typical coplanar waveguide transmission line structure 20 includes a signal transmission line 22 and two adjacent shielding lines 24 disposed on the same wiring level as the transmission line 22. The coplanar waveguide structure 20 is at a fixed distance from the silicon substrate 26. A third structure referred to as a microstrip transmission line having side shielding (i.e., having characteristics of both microstrip and coplanar structures) has also been used in existing transmission line structures.
As shown in FIG. 1(c), a typical microstrip transmission structure 30 with side shielding includes a signal transmission line 32, a ground plane 34 for shielding, and an interlayer dielectric material 36 therebetween. In addition, however, the shielding also includes shielding lines 38 disposed on the same wiring level as the signal transmission line 32. The shielding lines 38 are electrically contiguous with the ground plane 34 through conductively filled vias 40. As with the microstrip structure 10, the conventional coplanar elements are also surrounded by ILD material.
In each instance, the use of the ILD material as described above generates dielectric losses and reduces the Q-factor of the transmission lines in the BEOL interconnect. Accordingly, it would be desirable to create such shielded transmission line structures in conjunction with a lower dielectric material so as to improve the performance of the transmission lines.